File List

Here is a list of all documented files with brief descriptions:

[detail level 123]

hw
alu
alu.vhdl	File containing source code for the basic ALU
bus
bus_common.vhdl	File containing package declarations for the bus logic
bus_master.vhdl	Source code for the entity declaration of the master bus controller
bus_master_arch.vhdl	Source code for the architecture declaration of the master bus controller
bus_slave.vhdl	Source code for the slave bus controller entity declaration
bus_slave_arch.vhdl	Source code for the architecture declaration of the slave bus controller
tb_bus.vhdl	Testbench for the bus modules
cpu
tim_cpu.vhdl	Top file for the CPU module
mem
mem_dummy.vhdl	Source code for a dummy memory module used in simulations
sram_controller.vhdl	Source code for the SRAM memory controller used in synthesis
common.vhdl	Contains all constants, types and functions used across the architecture
instructions.vhdl	Contains definitions of all instruction opcodes and their byte size in memory
top_sim.vhdl	Top file for simulated version of the TIM Processor
top_synth.vhdl	Top file for synthesised version of the TIM Processor