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instructions.vhdl
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1 
8 
9 library ieee;
10 use ieee.std_logic_1164.ALL;
11 use ieee.numeric_std.ALL;
12 
13 use work.tim_common.opcode_length;
14 
16 package tim_instructions is
17 
19  constant opcode_LOADR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
20 
22  constant opcode_length_LOADR : integer := 4;
23 
25  constant opcode_LOADI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
26 
28  constant opcode_length_LOADI : integer := 4;
29 
31  constant opcode_STORI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
32 
34  constant opcode_length_STORI : integer := 4;
35 
37  constant opcode_STORR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
38 
40  constant opcode_length_STORR : integer := 4;
41 
43  constant opcode_PUSH : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
44 
46  constant opcode_length_PUSH : integer := 4;
47 
49  constant opcode_POP : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
50 
52  constant opcode_length_POP : integer := 4;
53 
55  constant opcode_MOVR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
56 
58  constant opcode_length_MOVR : integer := 4;
59 
61  constant opcode_MOVI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
62 
64  constant opcode_length_MOVI : integer := 4;
65 
67  constant opcode_JUMPR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
68 
70  constant opcode_length_JUMPR : integer := 4;
71 
73  constant opcode_JUMPI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
74 
76  constant opcode_length_JUMPI : integer := 4;
77 
79  constant opcode_CALLR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
80 
82  constant opcode_length_CALLR : integer := 4;
83 
85  constant opcode_CALLI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
86 
88  constant opcode_length_CALLI : integer := 4;
89 
91  constant opcode_RETURN: std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
92 
94  constant opcode_length_RETURN : integer := 4;
95 
97  constant opcode_TEST : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
98 
100  constant opcode_length_TEST : integer := 4;
101 
103  constant opcode_HALT : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
104 
106  constant opcode_length_HALT : integer := 4;
107 
109  constant opcode_ANDR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
110 
112  constant opcode_length_ANDR : integer := 4;
113 
115  constant opcode_NANDR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
116 
118  constant opcode_length_NANDR : integer := 4;
119 
121  constant opcode_ORR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
122 
124  constant opcode_length_ORR : integer := 4;
125 
127  constant opcode_NORR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
128 
130  constant opcode_length_NORR : integer := 4;
131 
133  constant opcode_XORR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
134 
136  constant opcode_length_XORR : integer := 4;
137 
139  constant opcode_LSLR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
140 
142  constant opcode_length_LSLR : integer := 4;
143 
145  constant opcode_LSRR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
146 
148  constant opcode_length_LSRR : integer := 4;
149 
151  constant opcode_NOTR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
152 
154  constant opcode_length_NOTR : integer := 4;
155 
157  constant opcode_ANDI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
158 
160  constant opcode_length_ANDI : integer := 4;
161 
163  constant opcode_NANDI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
164 
166  constant opcode_length_NANDI : integer := 4;
167 
169  constant opcode_ORI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
170 
172  constant opcode_length_ORI : integer := 4;
173 
175  constant opcode_NORI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
176 
178  constant opcode_length_NORI : integer := 4;
179 
181  constant opcode_XORI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
182 
184  constant opcode_length_XORI : integer := 4;
185 
187  constant opcode_LSLI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
188 
190  constant opcode_length_LSLI : integer := 4;
191 
193  constant opcode_LSRI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
194 
196  constant opcode_length_LSRI : integer := 4;
197 
199  constant opcode_IADDI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
200 
202  constant opcode_length_IADDI : integer := 4;
203 
205  constant opcode_ISUBI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
206 
208  constant opcode_length_ISUBI : integer := 4;
209 
211  constant opcode_IMULI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
212 
214  constant opcode_length_IMULI : integer := 4;
215 
217  constant opcode_IDIVI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
218 
220  constant opcode_length_IDIVI : integer := 4;
221 
223  constant opcode_IASRI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
224 
226  constant opcode_length_IASRI : integer := 4;
227 
229  constant opcode_IADDR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
230 
232  constant opcode_length_IADDR : integer := 4;
233 
235  constant opcode_ISUBR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
236 
238  constant opcode_length_ISUBR : integer := 4;
239 
241  constant opcode_IMULR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
242 
244  constant opcode_length_IMULR : integer := 4;
245 
247  constant opcode_IDIVR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
248 
250  constant opcode_length_IDIVR : integer := 4;
251 
253  constant opcode_IASRR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
254 
256  constant opcode_length_IASRR : integer := 4;
257 
259  constant opcode_FADDI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
260 
262  constant opcode_length_FADDI : integer := 4;
263 
265  constant opcode_FSUBI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
266 
268  constant opcode_length_FSUBI : integer := 4;
269 
271  constant opcode_FMULI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
272 
274  constant opcode_length_FMULI : integer := 4;
275 
277  constant opcode_FDIVI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
278 
280  constant opcode_length_FDIVI : integer := 4;
281 
283  constant opcode_FASRI : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
284 
286  constant opcode_length_FASRI : integer := 4;
287 
289  constant opcode_FADDR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
290 
292  constant opcode_length_FADDR : integer := 4;
293 
295  constant opcode_FSUBR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
296 
298  constant opcode_length_FSUBR : integer := 4;
299 
301  constant opcode_FMULR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
302 
304  constant opcode_length_FMULR : integer := 4;
305 
307  constant opcode_FDIVR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
308 
310  constant opcode_length_FDIVR : integer := 4;
311 
313  constant opcode_FASRR : std_logic_vector(opcode_length-1 downto 0) := std_logic_vector(to_unsigned(0, opcode_length));
314 
316  constant opcode_length_FASRR : integer := 4;
317 
318 end package;
tim_instructions.opcode_length_ORI
integer :=4 opcode_length_ORI
The length in bytes of the instruction.
Definition: instructions.vhdl:172
tim_instructions.opcode_ORI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_ORI
Bitwise OR two registers together.
Definition: instructions.vhdl:169
tim_instructions.opcode_length_STORR
integer :=4 opcode_length_STORR
The length in bytes of the instruction.
Definition: instructions.vhdl:40
tim_instructions
Package that contains declarations and definitions for all instruction opcodes and their lengths...
Definition: instructions.vhdl:16
tim_instructions.opcode_LSRI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_LSRI
Logical shift right the bits in register X by the immediate value.
Definition: instructions.vhdl:193
tim_instructions.opcode_TEST
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_TEST
Test two general or special registers and set comparison bits.
Definition: instructions.vhdl:97
tim_instructions.opcode_IMULI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_IMULI
Integer Multiply register X by immediate value.
Definition: instructions.vhdl:211
tim_common
Package header for all constants, functions and types used in TIM.
Definition: common.vhdl:14
tim_instructions.opcode_LSRR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_LSRR
Logical shift right the bits in register X by the value in register Y.
Definition: instructions.vhdl:145
tim_instructions.opcode_ANDI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_ANDI
Bitwise AND two registers together.
Definition: instructions.vhdl:157
tim_instructions.opcode_length_ANDI
integer :=4 opcode_length_ANDI
The length in bytes of the instruction.
Definition: instructions.vhdl:160
tim_instructions.opcode_LOADR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_LOADR
Load to register X from address in register Y with offset in register Z.
Definition: instructions.vhdl:19
tim_instructions.opcode_IADDI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_IADDI
Integer Add register X to immediate value.
Definition: instructions.vhdl:199
tim_instructions.opcode_length_IMULR
integer :=4 opcode_length_IMULR
The length in bytes of the instruction.
Definition: instructions.vhdl:244
tim_instructions.opcode_FMULI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FMULI
Floating point Multiply register X by immediate value.
Definition: instructions.vhdl:271
tim_instructions.opcode_length_HALT
integer :=4 opcode_length_HALT
The length in bytes of the instruction.
Definition: instructions.vhdl:106
tim_instructions.opcode_length_XORI
integer :=4 opcode_length_XORI
The length in bytes of the instruction.
Definition: instructions.vhdl:184
tim_instructions.opcode_length_LOADR
integer :=4 opcode_length_LOADR
The length in bytes of the instruction.
Definition: instructions.vhdl:22
tim_instructions.opcode_length_FMULR
integer :=4 opcode_length_FMULR
The length in bytes of the instruction.
Definition: instructions.vhdl:304
tim_instructions.opcode_CALLI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_CALLI
Call to function who's address is contained within instruction immediate.
Definition: instructions.vhdl:85
tim_instructions.opcode_LSLR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_LSLR
Logical shift left the bits in register X by the value in register Y.
Definition: instructions.vhdl:139
tim_instructions.opcode_length_MOVI
integer :=4 opcode_length_MOVI
The length in bytes of the instruction.
Definition: instructions.vhdl:64
tim_instructions.opcode_length_ISUBR
integer :=4 opcode_length_ISUBR
The length in bytes of the instruction.
Definition: instructions.vhdl:238
tim_instructions.opcode_length_CALLI
integer :=4 opcode_length_CALLI
The length in bytes of the instruction.
Definition: instructions.vhdl:88
tim_instructions.opcode_length_LSRI
integer :=4 opcode_length_LSRI
The length in bytes of the instruction.
Definition: instructions.vhdl:196
tim_instructions.opcode_IASRR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_IASRR
Integer Arithmetic shift register X right value in register Y.
Definition: instructions.vhdl:253
tim_instructions.opcode_length_ISUBI
integer :=4 opcode_length_ISUBI
The length in bytes of the instruction.
Definition: instructions.vhdl:208
tim_instructions.opcode_length_FSUBI
integer :=4 opcode_length_FSUBI
The length in bytes of the instruction.
Definition: instructions.vhdl:268
tim_instructions.opcode_length_STORI
integer :=4 opcode_length_STORI
The length in bytes of the instruction.
Definition: instructions.vhdl:34
tim_instructions.opcode_ISUBR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_ISUBR
Integer Subtract register X from register Y.
Definition: instructions.vhdl:235
tim_instructions.opcode_length_RETURN
integer :=4 opcode_length_RETURN
The length in bytes of the instruction.
Definition: instructions.vhdl:94
tim_instructions.opcode_length_IASRI
integer :=4 opcode_length_IASRI
The length in bytes of the instruction.
Definition: instructions.vhdl:226
tim_instructions.opcode_FSUBI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FSUBI
Floating point Subtract immediate value from register X.
Definition: instructions.vhdl:265
tim_instructions.opcode_length_LSRR
integer :=4 opcode_length_LSRR
The length in bytes of the instruction.
Definition: instructions.vhdl:148
tim_instructions.opcode_length_JUMPI
integer :=4 opcode_length_JUMPI
The length in bytes of the instruction.
Definition: instructions.vhdl:76
tim_instructions.opcode_length_FASRR
integer :=4 opcode_length_FASRR
The length in bytes of the instruction.
Definition: instructions.vhdl:316
tim_instructions.opcode_IDIVR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_IDIVR
Integer Divide register X by register Y.
Definition: instructions.vhdl:247
tim_instructions.opcode_ISUBI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_ISUBI
Integer Subtract immediate value from register X.
Definition: instructions.vhdl:205
tim_instructions.opcode_MOVI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_MOVI
Move immediate I into register X.
Definition: instructions.vhdl:61
tim_instructions.opcode_length_NORI
integer :=4 opcode_length_NORI
The length in bytes of the instruction.
Definition: instructions.vhdl:178
tim_instructions.opcode_ORR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_ORR
Bitwise OR two registers together.
Definition: instructions.vhdl:121
tim_instructions.opcode_length_PUSH
integer :=4 opcode_length_PUSH
The length in bytes of the instruction.
Definition: instructions.vhdl:46
tim_instructions.opcode_length_CALLR
integer :=4 opcode_length_CALLR
The length in bytes of the instruction.
Definition: instructions.vhdl:82
tim_instructions.opcode_STORI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_STORI
Store register X to address in register Y with offset in register Z.
Definition: instructions.vhdl:31
tim_instructions.opcode_FDIVR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FDIVR
Floating point Divide register X by register Y.
Definition: instructions.vhdl:307
tim_instructions.opcode_length_NANDR
integer :=4 opcode_length_NANDR
The length in bytes of the instruction.
Definition: instructions.vhdl:118
tim_instructions.opcode_MOVR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_MOVR
Move the content of register X into register Y.
Definition: instructions.vhdl:55
tim_instructions.opcode_length_FDIVI
integer :=4 opcode_length_FDIVI
The length in bytes of the instruction.
Definition: instructions.vhdl:280
tim_instructions.opcode_length_FSUBR
integer :=4 opcode_length_FSUBR
The length in bytes of the instruction.
Definition: instructions.vhdl:298
tim_instructions.opcode_ANDR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_ANDR
Bitwise AND two registers together.
Definition: instructions.vhdl:109
tim_instructions.opcode_length_JUMPR
integer :=4 opcode_length_JUMPR
The length in bytes of the instruction.
Definition: instructions.vhdl:70
tim_instructions.opcode_length_ORR
integer :=4 opcode_length_ORR
The length in bytes of the instruction.
Definition: instructions.vhdl:124
tim_instructions.opcode_length_FASRI
integer :=4 opcode_length_FASRI
The length in bytes of the instruction.
Definition: instructions.vhdl:286
tim_instructions.opcode_length_ANDR
integer :=4 opcode_length_ANDR
The length in bytes of the instruction.
Definition: instructions.vhdl:112
tim_instructions.opcode_length_XORR
integer :=4 opcode_length_XORR
The length in bytes of the instruction.
Definition: instructions.vhdl:136
tim_instructions.opcode_LSLI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_LSLI
Logical shift left the bits in register X by the immediate value.
Definition: instructions.vhdl:187
tim_instructions.opcode_FASRI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FASRI
Floating point Arithmetic shift register X right immediate value.
Definition: instructions.vhdl:283
tim_instructions.opcode_FADDR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FADDR
Floating point Add register X to register Y.
Definition: instructions.vhdl:289
tim_instructions.opcode_XORI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_XORI
Bitwise XOR two registers together.
Definition: instructions.vhdl:181
tim_instructions.opcode_FDIVI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FDIVI
Floating point Divide register X by immediate value.
Definition: instructions.vhdl:277
tim_instructions.opcode_length_POP
integer :=4 opcode_length_POP
The length in bytes of the instruction.
Definition: instructions.vhdl:52
tim_instructions.opcode_length_IDIVI
integer :=4 opcode_length_IDIVI
The length in bytes of the instruction.
Definition: instructions.vhdl:220
tim_instructions.opcode_length_NOTR
integer :=4 opcode_length_NOTR
The length in bytes of the instruction.
Definition: instructions.vhdl:154
tim_instructions.opcode_NANDI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_NANDI
Bitwise NAND two registers together.
Definition: instructions.vhdl:163
tim_instructions.opcode_STORR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_STORR
Store register X to address in register Y with immediate offset.
Definition: instructions.vhdl:37
tim_instructions.opcode_IDIVI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_IDIVI
Integer Divide register X by immediate value.
Definition: instructions.vhdl:217
tim_instructions.opcode_length_LSLI
integer :=4 opcode_length_LSLI
The length in bytes of the instruction.
Definition: instructions.vhdl:190
tim_instructions.opcode_length_IMULI
integer :=4 opcode_length_IMULI
The length in bytes of the instruction.
Definition: instructions.vhdl:214
tim_instructions.opcode_POP
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_POP
Pop element at top of stack into register X and increment the stack pointer.
Definition: instructions.vhdl:49
tim_instructions.opcode_length_FADDI
integer :=4 opcode_length_FADDI
The length in bytes of the instruction.
Definition: instructions.vhdl:262
tim_instructions.opcode_IASRI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_IASRI
Integer Arithmetic shift register X right immediate value.
Definition: instructions.vhdl:223
tim_instructions.opcode_LOADI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_LOADI
Load to register X from address in register Y with immediate offset.
Definition: instructions.vhdl:25
tim_instructions.opcode_FMULR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FMULR
Floating point Multiply register X by register Y.
Definition: instructions.vhdl:301
tim_instructions.opcode_FASRR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FASRR
Floating point Arithmetic shift register X right value in register Y.
Definition: instructions.vhdl:313
tim_instructions.opcode_length_LSLR
integer :=4 opcode_length_LSLR
The length in bytes of the instruction.
Definition: instructions.vhdl:142
tim_instructions.opcode_IADDR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_IADDR
Integer Add register X to register Y.
Definition: instructions.vhdl:229
tim_instructions.opcode_length_IASRR
integer :=4 opcode_length_IASRR
The length in bytes of the instruction.
Definition: instructions.vhdl:256
tim_instructions.opcode_NANDR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_NANDR
Bitwise NAND two registers together.
Definition: instructions.vhdl:115
tim_instructions.opcode_XORR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_XORR
Bitwise XOR two registers together.
Definition: instructions.vhdl:133
tim_instructions.opcode_length_NANDI
integer :=4 opcode_length_NANDI
The length in bytes of the instruction.
Definition: instructions.vhdl:166
tim_instructions.opcode_length_FMULI
integer :=4 opcode_length_FMULI
The length in bytes of the instruction.
Definition: instructions.vhdl:274
tim_instructions.opcode_NOTR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_NOTR
Bitwise invert the specificed register.
Definition: instructions.vhdl:151
tim_instructions.opcode_PUSH
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_PUSH
Push register X onto the top of the stack and decrement the stack pointer.
Definition: instructions.vhdl:43
tim_instructions.opcode_JUMPR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_JUMPR
Jump to address contained within register X.
Definition: instructions.vhdl:67
tim_instructions.opcode_FADDI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FADDI
Floating point Add register X to immediate value.
Definition: instructions.vhdl:259
tim_instructions.opcode_HALT
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_HALT
Stop processing and wait to be reset.
Definition: instructions.vhdl:103
tim_instructions.opcode_NORI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_NORI
Bitwise NOR two registers together.
Definition: instructions.vhdl:175
tim_instructions.opcode_length_IADDI
integer :=4 opcode_length_IADDI
The length in bytes of the instruction.
Definition: instructions.vhdl:202
tim_instructions.opcode_FSUBR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_FSUBR
Floating point Subtract register X from register Y.
Definition: instructions.vhdl:295
tim_instructions.opcode_JUMPI
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_JUMPI
Jump to address contained within instruction immediate.
Definition: instructions.vhdl:73
tim_instructions.opcode_length_FDIVR
integer :=4 opcode_length_FDIVR
The length in bytes of the instruction.
Definition: instructions.vhdl:310
tim_instructions.opcode_length_NORR
integer :=4 opcode_length_NORR
The length in bytes of the instruction.
Definition: instructions.vhdl:130
tim_instructions.opcode_NORR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_NORR
Bitwise NOR two registers together.
Definition: instructions.vhdl:127
tim_instructions.opcode_length_TEST
integer :=4 opcode_length_TEST
The length in bytes of the instruction.
Definition: instructions.vhdl:100
tim_instructions.opcode_length_IDIVR
integer :=4 opcode_length_IDIVR
The length in bytes of the instruction.
Definition: instructions.vhdl:250
tim_instructions.opcode_length_FADDR
integer :=4 opcode_length_FADDR
The length in bytes of the instruction.
Definition: instructions.vhdl:292
tim_instructions.opcode_IMULR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_IMULR
Integer Multiply register X by register Y.
Definition: instructions.vhdl:241
tim_instructions.opcode_length_IADDR
integer :=4 opcode_length_IADDR
The length in bytes of the instruction.
Definition: instructions.vhdl:232
tim_instructions.opcode_length_LOADI
integer :=4 opcode_length_LOADI
The length in bytes of the instruction.
Definition: instructions.vhdl:28
tim_instructions.opcode_length_MOVR
integer :=4 opcode_length_MOVR
The length in bytes of the instruction.
Definition: instructions.vhdl:58
tim_instructions.opcode_CALLR
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_CALLR
Call to function who's address is contained within register X.
Definition: instructions.vhdl:79
tim_instructions.opcode_RETURN
std_logic_vector (opcode_length - 1 downto 0) :=std_logic_vector (to_unsigned (0 ,opcode_length)) opcode_RETURN
Return from the last function call.
Definition: instructions.vhdl:91