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bus_slave_arch.vhdl
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1 
7 
8 
9 library ieee;
10 use ieee.std_logic_1164.ALL;
11 use ieee.numeric_std.ALL;
12 
14 use work.tim_bus.tim_bus_data_width;
16 use work.tim_bus.tim_bus_master_state;
17 
18 
19 
21 architecture tim_bus_slave_rtl of tim_bus_slave is
22 
24  signal current_state : tim_bus_master_state := BUS_RESET;
26  signal next_state : tim_bus_master_state := IDLE;
27 
29  signal internal_address_lines : std_logic_vector(data_width-1 downto 0);
31  signal internal_data_lines : std_logic_vector(data_width-1 downto 0);
32 
33 begin
34 
36  state_machine_progress : process (clk, reset)
37  begin
38  if(reset='1') then
39  current_state <= BUS_RESET;
40  elsif(clk'event and clk = '1') then
41  current_state <= next_state;
42  end if;
43  end process state_machine_progress;
44 
46  state_machine_next_state : process(clk,bus_valid, bus_lines, bus_read_write)
47  begin
48 
49  case current_state is
50 
51  when BUS_RESET =>
52  next_state <= IDLE;
53 
54  when IDLE =>
55  if(bus_valid = '1' and
56  to_integer(unsigned(bus_lines)) >= address_range_bottom and
57  to_integer(unsigned(bus_lines)) <= address_range_top) then
58  next_state <= REQ;
59  else
60  next_state <= IDLE;
61  end if;
62 
63  when REQ =>
64  if(bus_read_write = '1') then
65  next_state <= WRITE;
66  else
67  next_state <= READ;
68  end if;
69 
70  when READ =>
71  if(req_done = '1') then
72  next_state <= IDLE;
73  else
74  next_state <= READ;
75  end if;
76 
77  when WRITE =>
78  if(req_done = '1') then
79  next_state <= IDLE;
80  else
81  next_state <= READ;
82  end if;
83 
84  end case;
85 
86  end process state_machine_next_state;
87 
88 
90  bus_outputs : process(current_state, req_data_lines)
91  begin
92 
93  case current_state is
94 
95  when BUS_RESET =>
96  bus_lines <= (others => 'Z');
97  bus_enable <= 'Z';
98  internal_address_lines <= (others => '0');
99 
100  when IDLE =>
101  bus_lines <= (others => 'Z');
102  bus_enable <= 'Z';
103  internal_address_lines <= internal_address_lines;
104 
105  when REQ =>
106  bus_lines <= (others => 'Z');
107  bus_enable <= '1';
108  internal_address_lines <= bus_lines;
109 
110  when READ =>
111  bus_lines <= req_data_lines;
112  bus_enable <= '0';
113  internal_address_lines <= internal_address_lines;
114 
115  when WRITE =>
116  bus_lines <= (others => 'Z');
117  bus_enable <= '1';
118  internal_address_lines <= internal_address_lines;
119 
120  end case;
121 
122  end process bus_outputs;
123 
125  device_outputs: process(current_state, bus_lines, internal_address_lines)
126  begin
127 
128  case current_state is
129 
130  when BUS_RESET =>
131  req_read_write <= '0';
132  req_address_lines <= (others => '0');
133  req_data_lines <= (others => 'Z');
134  req_pending <= '0';
135 
136  when IDLE =>
137  req_read_write <= '0';
138  req_address_lines <= (others => '0');
139  req_data_lines <= (others => 'Z');
140  req_pending <= '0';
141 
142  when REQ =>
143  req_read_write <= bus_read_write;
144  req_address_lines <= internal_address_lines;
145  req_data_lines <= (others => 'Z');
146  req_pending <= '1';
147 
148  when READ =>
149  req_read_write <= bus_read_write;
150  req_address_lines <= internal_address_lines;
151  req_data_lines <= (others => 'Z');
152  req_pending <= '1';
153 
154  when WRITE =>
155  req_read_write <= bus_read_write;
156  req_address_lines <= internal_address_lines;
157  req_data_lines <= internal_data_lines;
158  req_pending <= '1';
159 
160  end case;
161 
162  end process device_outputs;
163 
164 end architecture tim_bus_slave_rtl;
tim_bus_slave.tim_bus_slave_rtl.state_machine_progress
state_machine_progressclk,reset
Responsible for the synchronous state transitions and asynchronous resets.
Definition: bus_slave_arch.vhdl:36
tim_bus_slave.tim_bus_slave_rtl.state_machine_next_state
state_machine_next_stateclk,bus_valid,bus_lines,bus_read_write
Responsible for determining the next state of the statemachine.
Definition: bus_slave_arch.vhdl:46
tim_bus_slave.address_range_bottom
address_range_bottominteger :=0
The bottomof the range of addresses to which this slave controller will respond to requests...
Definition: bus_slave.vhdl:26
tim_bus_slave
The bus slave controller module which responds to requests from the master.
Definition: bus_slave.vhdl:17
tim_bus_slave.bus_read_write
in bus_read_writestd_logic
High if this transaction is a write, low if it is a read.
Definition: bus_slave.vhdl:44
tim_bus_slave.tim_bus_slave_rtl.current_state
tim_bus_master_state :=BUS_RESET current_state
The current state of the controller.
Definition: bus_slave_arch.vhdl:24
tim_bus_slave.req_address_lines
out req_address_linesstd_logic_vector (data_width - 1 downto 0)
The address the bus transaction is targeting within the device.
Definition: bus_slave.vhdl:50
tim_bus_slave.data_width
data_widthinteger :=tim_bus_data_width
The number of data and address lines.
Definition: bus_slave.vhdl:20
tim_bus_slave.bus_valid
in bus_validstd_logic
Used to assert data written by the bus master to bus_lines is valid.
Definition: bus_slave.vhdl:38
tim_bus_slave.reset
in resetstd_logic
Asynchonous reset signal.
Definition: bus_slave.vhdl:32
tim_bus_slave.tim_bus_slave_rtl.bus_outputs
bus_outputscurrent_state,req_data_lines
Responsible for driving the bus outputs based on the current state of the controller.
Definition: bus_slave_arch.vhdl:90
tim_bus_slave.address_range_top
address_range_topinteger :=1023
The top of the range of addresses to which this slave controller will respond to requests.
Definition: bus_slave.vhdl:23
tim_bus_slave.tim_bus_slave_rtl.device_outputs
device_outputscurrent_state,bus_lines,internal_address_lines
Responsible for driving the bus device outputs based on the current state of the controller.
Definition: bus_slave_arch.vhdl:125
tim_bus_slave.tim_bus_slave_rtl.internal_data_lines
std_logic_vector (data_width - 1 downto 0) internal_data_lines
Internal storage for the data of a transaction.
Definition: bus_slave_arch.vhdl:31
tim_bus_slave.tim_bus_slave_rtl.internal_address_lines
std_logic_vector (data_width - 1 downto 0) internal_address_lines
Internal storage for the address of a transaction.
Definition: bus_slave_arch.vhdl:29
tim_bus_slave.req_read_write
out req_read_writestd_logic
Whether this is a read or write transaction the device must respond to.
Definition: bus_slave.vhdl:47
tim_bus_slave.bus_enable
out bus_enablestd_logic
Used to assert that the slave has read the bus lines and they can be updated.
Definition: bus_slave.vhdl:41
tim_bus_slave.clk
in clkstd_logic
The main system clock.
Definition: bus_slave.vhdl:30
tim_bus_slave.req_done
in req_donestd_logic
Tells the controller the device has written/read all values from the address and data lines and can f...
Definition: bus_slave.vhdl:59
tim_bus_slave.req_data_lines
inout req_data_linesstd_logic_vector (data_width - 1 downto 0)
The data the transaction needs. Either read data is put onto this or write data is taken off it...
Definition: bus_slave.vhdl:53
tim_bus_slave.tim_bus_slave_rtl.next_state
tim_bus_master_state :=IDLE next_state
The next state of the controller.
Definition: bus_slave_arch.vhdl:26
tim_bus_slave.req_pending
out req_pendingstd_logic
Tells the host device a bus request needs dealing with.
Definition: bus_slave.vhdl:56
tim_bus_slave.bus_lines
inout bus_linesstd_logic_vector (data_width - 1 downto 0)
The lines which carry data and addresses;.
Definition: bus_slave.vhdl:35
tim_bus
This package contains entity declarations and shared constant values for the bus logic modules...
Definition: bus_common.vhdl:11