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T.I.M | Hardware Documentation
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T.I.M | Hardware Documentation
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The synthesisable architecture of the tim bus slave controller. More...
Processes | |
| state_machine_progress | ( clk , reset ) |
| Responsible for the synchronous state transitions and asynchronous resets. | |
| state_machine_next_state | ( clk , bus_valid , bus_lines , bus_read_write ) |
| Responsible for determining the next state of the statemachine. | |
| bus_outputs | ( current_state , req_data_lines ) |
| Responsible for driving the bus outputs based on the current state of the controller. | |
| device_outputs | ( current_state , bus_lines , internal_address_lines ) |
| Responsible for driving the bus device outputs based on the current state of the controller. | |
Libraries | |
| ieee | |
Use Clauses | |
| ieee.std_logic_1164.all | |
| ieee.numeric_std.all | |
| work.tim_bus.tim_bus_data_width | |
| Imported from tim_bus package,. | |
| work.tim_bus.tim_bus_master_state | |
| Imported from tim_bus package,. | |
Signals | |
| current_state | tim_bus_master_state := BUS_RESET |
| The current state of the controller. | |
| next_state | tim_bus_master_state := IDLE |
| The next state of the controller. | |
| internal_address_lines | std_logic_vector ( data_width - 1 downto 0 ) |
| Internal storage for the address of a transaction. | |
| internal_data_lines | std_logic_vector ( data_width - 1 downto 0 ) |
| Internal storage for the data of a transaction. | |
The synthesisable architecture of the tim bus slave controller.
Definition at line 21 of file bus_slave_arch.vhdl.