The bus slave controller module which responds to requests from the master. More...

Inheritance diagram for tim_bus_slave:

Entities
tim_bus_slave_rtl	architecture
	The synthesisable architecture of the tim bus slave controller. More...

Libraries
ieee

Use Clauses
ieee.std_logic_1164.all
ieee.numeric_std.all
work.tim_bus.tim_bus_data_width
	Imported from tim_bus package,.

Generics
data_width	integer := tim_bus_data_width
	The number of data and address lines.
address_range_top	integer := 1023
	The top of the range of addresses to which this slave controller will respond to requests.
address_range_bottom	integer := 0
	The bottomof the range of addresses to which this slave controller will respond to requests.

Ports
clk	in std_logic
	The main system clock.
reset	in std_logic
	Asynchonous reset signal.
bus_lines	inout std_logic_vector ( data_width - 1 downto 0 )
	The lines which carry data and addresses;.
bus_valid	in std_logic
	Used to assert data written by the bus master to bus_lines is valid.
bus_enable	out std_logic
	Used to assert that the slave has read the bus lines and they can be updated.
bus_read_write	in std_logic
	High if this transaction is a write, low if it is a read.
req_read_write	out std_logic
	Whether this is a read or write transaction the device must respond to.
req_address_lines	out std_logic_vector ( data_width - 1 downto 0 )
	The address the bus transaction is targeting within the device.
req_data_lines	inout std_logic_vector ( data_width - 1 downto 0 )
	The data the transaction needs. Either read data is put onto this or write data is taken off it.
req_pending	out std_logic
	Tells the host device a bus request needs dealing with.
req_done	in std_logic
	Tells the controller the device has written/read all values from the address and data lines and can finish the request.

Detailed Description

The bus slave controller module which responds to requests from the master.

Definition at line 17 of file bus_slave.vhdl.

The documentation for this class was generated from the following file:

Entities