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bus_slave.vhdl
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1 
7 
8 library ieee;
9 use ieee.std_logic_1164.ALL;
10 use ieee.numeric_std.ALL;
11 
13 use work.tim_bus.tim_bus_data_width;
14 
15 
17 entity tim_bus_slave is
18  generic(
20  data_width : integer := tim_bus_data_width;
21 
23  address_range_top : integer := 1023;
24 
26  address_range_bottom : integer := 0
27  );
28  port(
30  clk : in std_logic;
32  reset : in std_logic;
33 
35  bus_lines : inout std_logic_vector(data_width-1 downto 0);
36 
38  bus_valid : in std_logic;
39 
41  bus_enable : out std_logic;
42 
44  bus_read_write : in std_logic;
45 
47  req_read_write : out std_logic;
48 
50  req_address_lines : out std_logic_vector(data_width-1 downto 0);
51 
53  req_data_lines : inout std_logic_vector(data_width-1 downto 0);
54 
56  req_pending : out std_logic;
57 
59  req_done : in std_logic
60  );
61 end entity tim_bus_slave;
tim_bus_slave.address_range_bottom
address_range_bottominteger :=0
The bottomof the range of addresses to which this slave controller will respond to requests...
Definition: bus_slave.vhdl:26
tim_bus_slave
The bus slave controller module which responds to requests from the master.
Definition: bus_slave.vhdl:17
tim_bus_slave.bus_read_write
in bus_read_writestd_logic
High if this transaction is a write, low if it is a read.
Definition: bus_slave.vhdl:44
tim_bus_slave.req_address_lines
out req_address_linesstd_logic_vector (data_width - 1 downto 0)
The address the bus transaction is targeting within the device.
Definition: bus_slave.vhdl:50
tim_bus_slave.data_width
data_widthinteger :=tim_bus_data_width
The number of data and address lines.
Definition: bus_slave.vhdl:20
tim_bus_slave.bus_valid
in bus_validstd_logic
Used to assert data written by the bus master to bus_lines is valid.
Definition: bus_slave.vhdl:38
tim_bus_slave.reset
in resetstd_logic
Asynchonous reset signal.
Definition: bus_slave.vhdl:32
tim_bus_slave.address_range_top
address_range_topinteger :=1023
The top of the range of addresses to which this slave controller will respond to requests.
Definition: bus_slave.vhdl:23
tim_bus_slave.req_read_write
out req_read_writestd_logic
Whether this is a read or write transaction the device must respond to.
Definition: bus_slave.vhdl:47
tim_bus_slave.bus_enable
out bus_enablestd_logic
Used to assert that the slave has read the bus lines and they can be updated.
Definition: bus_slave.vhdl:41
tim_bus_slave.clk
in clkstd_logic
The main system clock.
Definition: bus_slave.vhdl:30
tim_bus_slave.req_done
in req_donestd_logic
Tells the controller the device has written/read all values from the address and data lines and can f...
Definition: bus_slave.vhdl:59
tim_bus_slave.req_data_lines
inout req_data_linesstd_logic_vector (data_width - 1 downto 0)
The data the transaction needs. Either read data is put onto this or write data is taken off it...
Definition: bus_slave.vhdl:53
tim_bus_slave.req_pending
out req_pendingstd_logic
Tells the host device a bus request needs dealing with.
Definition: bus_slave.vhdl:56
tim_bus_slave.bus_lines
inout bus_linesstd_logic_vector (data_width - 1 downto 0)
The lines which carry data and addresses;.
Definition: bus_slave.vhdl:35
tim_bus
This package contains entity declarations and shared constant values for the bus logic modules...
Definition: bus_common.vhdl:11