doc/hw/bus__master_8vhdl_source.html

 library ieee;

 use ieee.std_logic_1164.ALL;

 use ieee.numeric_std.ALL;


 use work.tim_bus.tim_bus_data_width;


 entity tim_bus_master is

     generic(

         data_width  : integer := tim_bus_data_width

     );

     port(

         clk             : in    std_logic;

         reset           : in    std_logic;


         bus_lines       : inout std_logic_vector(data_width-1 downto 0);


         bus_valid       : out   std_logic;


         bus_enable      : in    std_logic;


         bus_read_write  : out   std_logic;


         req_data_lines      : inout std_logic_vector(data_width-1 downto 0);


         req_read_write      : in    std_logic;


         req_address_lines   : in    std_logic_vector(data_width-1 downto 0);


         req_pending         : in    std_logic;


         req_acknowledge     : out   std_logic

     );

 end entity tim_bus_master;

tim_bus_master.bus_read_write
out bus_read_writestd_logic
High if this transaction is a write, low if it is a read.
Definition: bus_master.vhdl:38

tim_bus_master.req_read_write
in req_read_writestd_logic
Tells the controller if this is a read or write transaction. High == write, low == read...
Definition: bus_master.vhdl:44

tim_bus_master.req_address_lines
in req_address_linesstd_logic_vector (data_width - 1   downto   0)
Addresses for read and write operations are placed on these lines.
Definition: bus_master.vhdl:47

tim_bus_master.req_pending
in req_pendingstd_logic
This is put high to tell the controller a request is pending.
Definition: bus_master.vhdl:50

tim_bus_master.reset
in resetstd_logic
Asynchonous reset signal.
Definition: bus_master.vhdl:26

tim_bus_master.bus_lines
inout bus_linesstd_logic_vector (data_width - 1   downto   0)
The lines which carry data and addresses;.
Definition: bus_master.vhdl:29

tim_bus_master.clk
in clkstd_logic
The main system clock.
Definition: bus_master.vhdl:24

tim_bus_master.bus_valid
out bus_validstd_logic
Used to assert data written by the bus master to bus_lines is valid.
Definition: bus_master.vhdl:32

tim_bus_master.req_acknowledge
out req_acknowledgestd_logic
Definition: bus_master.vhdl:54

tim_bus_master.req_data_lines
inout req_data_linesstd_logic_vector (data_width - 1   downto   0)
Request write data is placed on these lines.
Definition: bus_master.vhdl:41

tim_bus_master.data_width
data_widthinteger :=tim_bus_data_width
The number of data and address lines.
Definition: bus_master.vhdl:20

tim_bus_master
The bus master controller module which arbitrates bus requests and responses.
Definition: bus_master.vhdl:17

tim_bus
This package contains entity declarations and shared constant values for the bus logic modules...
Definition: bus_common.vhdl:11

tim_bus_master.bus_enable
in bus_enablestd_logic
Used to assert that the slave has read the bus lines and they can be updated.
Definition: bus_master.vhdl:35