The bus master controller module which arbitrates bus requests and responses. More...

Inheritance diagram for tim_bus_master:

Entities
tim_bus_master_rtl	architecture
	RTL & synthesisable architecture of the bus master controller. More...

Libraries
ieee

Use Clauses
ieee.std_logic_1164.all
ieee.numeric_std.all
work.tim_bus.tim_bus_data_width
	Imported from tim_bus package,.

Generics
data_width	integer := tim_bus_data_width
	The number of data and address lines.

Ports
clk	in std_logic
	The main system clock.
reset	in std_logic
	Asynchonous reset signal.
bus_lines	inout std_logic_vector ( data_width - 1 downto 0 )
	The lines which carry data and addresses;.
bus_valid	out std_logic
	Used to assert data written by the bus master to bus_lines is valid.
bus_enable	in std_logic
	Used to assert that the slave has read the bus lines and they can be updated.
bus_read_write	out std_logic
	High if this transaction is a write, low if it is a read.
req_data_lines	inout std_logic_vector ( data_width - 1 downto 0 )
	Request write data is placed on these lines.
req_read_write	in std_logic
	Tells the controller if this is a read or write transaction. High == write, low == read.
req_address_lines	in std_logic_vector ( data_width - 1 downto 0 )
	Addresses for read and write operations are placed on these lines.
req_pending	in std_logic
	This is put high to tell the controller a request is pending.
req_acknowledge	out std_logic

Detailed Description

The bus master controller module which arbitrates bus requests and responses.

Definition at line 17 of file bus_master.vhdl.

Member Data Documentation

req_acknowledge out std_logic

Port

This is put high to tell the requestor that the request has been accepted. When it goes low again, This signals that the response is available

Definition at line 54 of file bus_master.vhdl.

The documentation for this class was generated from the following file: