RTL & synthesisable architecture of the bus master controller. More...

Processes
state_machine_progress	( clk , reset )
	Responsible for the synchronous state transitions and asynchronous resets.
state_machine_next_state	( clk , bus_enable , req_read_write , req_pending )
	Responsible for determining the next state of the statemachine.
bus_outputs	( current_state , req_data_lines , req_address_lines , req_read_write )
	Responsible for driving the bus outputs based on the current state of the controller.
requestor_outputs	( current_state , bus_lines )
	Responsible for driving the requestor outputs based on the current state of the controller.

Libraries
ieee

Use Clauses
ieee.std_logic_1164.all
ieee.numeric_std.all
work.tim_bus.tim_bus_data_width
	Imported from tim_bus package,.
work.tim_bus.tim_bus_master_state
	Imported from tim_bus package,.

Signals
current_state	tim_bus_master_state := BUS_RESET
	The current state of the controller.
next_state	tim_bus_master_state := IDLE
	The next state of the controller.

Detailed Description

RTL & synthesisable architecture of the bus master controller.

Definition at line 19 of file bus_master_arch.vhdl.

The documentation for this class was generated from the following file:

Processes