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bus_master_arch.vhdl
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1 
7 
8 
9 library ieee;
10 use ieee.std_logic_1164.ALL;
11 use ieee.numeric_std.ALL;
12 
14 use work.tim_bus.tim_bus_data_width;
16 use work.tim_bus.tim_bus_master_state;
17 
19 architecture tim_bus_master_rtl of tim_bus_master is
20 
22  signal current_state : tim_bus_master_state := BUS_RESET;
24  signal next_state : tim_bus_master_state := IDLE;
25 
26 begin
27 
29  state_machine_progress : process (clk, reset)
30  begin
31  if(reset='1') then
32  current_state <= BUS_RESET;
33  elsif(clk'event and clk = '1') then
34  current_state <= next_state;
35  end if;
36  end process state_machine_progress;
37 
38 
40  state_machine_next_state : process(clk, bus_enable, req_read_write, req_pending)
41  begin
42 
43  case current_state is
44 
45  when BUS_RESET =>
46  next_state <= IDLE;
47 
48  when IDLE =>
49  if(req_pending = '1') then
50  next_state <= REQ;
51  else
52  next_state <= IDLE;
53  end if;
54 
55  when REQ =>
56  if(bus_enable = '1' and req_read_write = '0') then
57  next_state <= READ;
58  elsif(bus_enable = '1' and req_read_write = '1') then
59  next_state <= WRITE;
60  else
61  next_state <= REQ;
62  end if;
63 
64  when READ =>
65  if(bus_enable = '0') then
66  next_state <= IDLE;
67  else
68  next_state <= READ;
69  end if;
70 
71  when WRITE =>
72  if(bus_enable = '0') then
73  next_state <= IDLE;
74  else
75  next_state <= READ;
76  end if;
77 
78  end case;
79 
80  end process state_machine_next_state;
81 
82 
84  bus_outputs : process(current_state, req_data_lines, req_address_lines, req_read_write)
85 
86  begin
87 
88  case current_state is
89 
90  when BUS_RESET =>
91  bus_lines <= (others => 'Z');
92  bus_valid <= '0';
93  bus_read_write <= '0';
94 
95  when IDLE =>
96  bus_lines <= (others => 'Z');
97  bus_valid <= '0';
98  bus_read_write <= '0';
99 
100  when REQ =>
101  bus_lines <= req_address_lines;
102  bus_valid <= '1';
103  bus_read_write <= req_read_write;
104 
105  when READ =>
106  bus_lines <= (others => 'Z');
107  bus_valid <= '1';
108  bus_read_write <= req_read_write;
109 
110  when WRITE =>
111  bus_lines <= req_data_lines;
112  bus_valid <= '0';
113  bus_read_write <= req_read_write;
114 
115  end case;
116 
117  end process bus_outputs;
118 
120  requestor_outputs: process(current_state, bus_lines)
121 
122  begin
123 
124  case current_state is
125 
126  when BUS_RESET =>
127  req_data_lines <= (others => 'Z');
128  req_acknowledge <= '0';
129 
130  when IDLE =>
131  req_data_lines <= (others => 'Z');
132  req_acknowledge <= '0';
133 
134  when REQ =>
135  req_data_lines <= (others => 'Z');
136  req_acknowledge <= '1';
137 
138  when READ =>
139  req_data_lines <= bus_lines;
140  req_acknowledge <= '1';
141 
142  when WRITE =>
143  req_data_lines <= (others => 'Z');
144  req_acknowledge <= '1';
145 
146  end case;
147 
148  end process requestor_outputs;
149 
150 end architecture tim_bus_master_rtl;
tim_bus_master.tim_bus_master_rtl.state_machine_next_state
state_machine_next_stateclk,bus_enable,req_read_write,req_pending
Responsible for determining the next state of the statemachine.
Definition: bus_master_arch.vhdl:40
tim_bus_master.tim_bus_master_rtl.state_machine_progress
state_machine_progressclk,reset
Responsible for the synchronous state transitions and asynchronous resets.
Definition: bus_master_arch.vhdl:29
tim_bus_master.bus_read_write
out bus_read_writestd_logic
High if this transaction is a write, low if it is a read.
Definition: bus_master.vhdl:38
tim_bus_master.tim_bus_master_rtl.requestor_outputs
requestor_outputscurrent_state,bus_lines
Responsible for driving the requestor outputs based on the current state of the controller.
Definition: bus_master_arch.vhdl:120
tim_bus_master.tim_bus_master_rtl.next_state
tim_bus_master_state :=IDLE next_state
The next state of the controller.
Definition: bus_master_arch.vhdl:24
tim_bus_master.req_read_write
in req_read_writestd_logic
Tells the controller if this is a read or write transaction. High == write, low == read...
Definition: bus_master.vhdl:44
tim_bus_master.req_address_lines
in req_address_linesstd_logic_vector (data_width - 1 downto 0)
Addresses for read and write operations are placed on these lines.
Definition: bus_master.vhdl:47
tim_bus_master.req_pending
in req_pendingstd_logic
This is put high to tell the controller a request is pending.
Definition: bus_master.vhdl:50
tim_bus_master.reset
in resetstd_logic
Asynchonous reset signal.
Definition: bus_master.vhdl:26
tim_bus_master.tim_bus_master_rtl.current_state
tim_bus_master_state :=BUS_RESET current_state
The current state of the controller.
Definition: bus_master_arch.vhdl:22
tim_bus_master.bus_lines
inout bus_linesstd_logic_vector (data_width - 1 downto 0)
The lines which carry data and addresses;.
Definition: bus_master.vhdl:29
tim_bus_master.clk
in clkstd_logic
The main system clock.
Definition: bus_master.vhdl:24
tim_bus_master.bus_valid
out bus_validstd_logic
Used to assert data written by the bus master to bus_lines is valid.
Definition: bus_master.vhdl:32
tim_bus_master.tim_bus_master_rtl.bus_outputs
bus_outputscurrent_state,req_data_lines,req_address_lines,req_read_write
Responsible for driving the bus outputs based on the current state of the controller.
Definition: bus_master_arch.vhdl:84
tim_bus_master.req_acknowledge
out req_acknowledgestd_logic
Definition: bus_master.vhdl:54
tim_bus_master.req_data_lines
inout req_data_linesstd_logic_vector (data_width - 1 downto 0)
Request write data is placed on these lines.
Definition: bus_master.vhdl:41
tim_bus_master
The bus master controller module which arbitrates bus requests and responses.
Definition: bus_master.vhdl:17
tim_bus
This package contains entity declarations and shared constant values for the bus logic modules...
Definition: bus_common.vhdl:11
tim_bus_master.bus_enable
in bus_enablestd_logic
Used to assert that the slave has read the bus lines and they can be updated.
Definition: bus_master.vhdl:35