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tb_bus.vhdl
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1 
7 
8 
9 library ieee;
10 use ieee.std_logic_1164.ALL;
11 use ieee.numeric_std.ALL;
12 
14 use work.tim_bus.tim_bus_data_width;
16 use work.tim_bus.tim_bus_burst_width;
17 
19 entity tb_bus is
20 end entity tb_bus;
21 
22 
24 architecture testbench of tb_bus is
25 
26 
28 component tim_bus_master is
29  generic(
31  data_width : integer := tim_bus_data_width
32  );
33  port(
35  clk : in std_logic;
37  reset : in std_logic;
39  bus_lines : inout std_logic_vector(data_width-1 downto 0);
41  bus_valid : out std_logic;
43  bus_enable : in std_logic;
45  bus_read_write : out std_logic;
47  req_data_lines : inout std_logic_vector(data_width-1 downto 0);
49  req_read_write : in std_logic;
51  req_address_lines : in std_logic_vector(data_width-1 downto 0);
53  req_pending : in std_logic;
55  req_acknowledge : out std_logic
56  );
57 end component tim_bus_master;
58 
59 
61 component tim_bus_slave is
62  generic(
64  data_width : integer := tim_bus_data_width;
66  address_range_top : integer := 1023;
68  address_range_bottom : integer := 0
69  );
70  port(
72  clk : in std_logic;
74  reset : in std_logic;
76  bus_lines : inout std_logic_vector(data_width-1 downto 0);
78  bus_valid : in std_logic;
80  bus_enable : out std_logic;
82  bus_read_write : in std_logic;
84  req_read_write : out std_logic;
86  req_address_lines : out std_logic_vector(data_width-1 downto 0);
88  req_data_lines : inout std_logic_vector(data_width-1 downto 0);
90  req_pending : out std_logic;
92  req_done : in std_logic
93  );
94 end component tim_bus_slave;
95 
97  signal tb_clk : std_logic := '0';
99  signal tb_reset : std_logic := '1';
100 
101  --
102  -- These are all the system bus signals.
103  --
104  signal bus_lines : std_logic_vector(tim_bus_data_width-1 downto 0) := (others => 'Z');
105  signal bus_valid : std_logic := '0';
106  signal bus_enable : std_logic := '0';
107  signal bus_read_write : std_logic := '0';
108 
109 
110  --
111  -- These are the master device signals.
112  --
113 
114  signal master_data : std_logic_vector(tim_bus_data_width-1 downto 0) := (others => '1');
115  signal master_address : std_logic_vector(tim_bus_data_width-1 downto 0) := (others => '0');
116  signal master_read_write : std_logic := '0';
117  signal master_pending : std_logic := '0';
118  signal master_acknowledge : std_logic := '0';
119 
120  --
121  -- These are the slave device signals.
122  --
123 
124  signal slave_0_read_write : std_logic := '0';
125  signal slave_0_address : std_logic_vector(tim_bus_data_width-1 downto 0) := (others => 'Z');
126  signal slave_0_data : std_logic_vector(tim_bus_data_width-1 downto 0) := (others => '0');
127  signal slave_0_pending : std_logic := '0';
128  signal slave_0_done : std_logic := '0';
129 
130  signal slave_1_read_write : std_logic := '0';
131  signal slave_1_address : std_logic_vector(tim_bus_data_width-1 downto 0) := (others => 'Z');
132  signal slave_1_data : std_logic_vector(tim_bus_data_width-1 downto 0) := (others => '1');
133  signal slave_1_pending : std_logic := '0';
134  signal slave_1_done : std_logic := '0';
135 
136  --
137  -- Testbench signals.
138  --
139 
140 begin
141 
142  --
143  -- Continuous assignments
144  --
145 
146  tb_clk <= not tb_clk after 20 ns;
147  tb_reset <= '0' after 50 ns;
148 
150  master_control : process(tb_clk, tb_reset, master_acknowledge)
151  begin
152 
153  if(tb_reset = '1') then
154 
155  master_pending <= '0';
156 
157  elsif(tb_clk'event and master_acknowledge = '0' and master_pending = '0') then
158 
159  master_pending <= '1';
160  master_address <= std_logic_vector(unsigned(master_address)+128);
161 
162  elsif(tb_clk'event and master_acknowledge = '1') then
163 
164  master_pending <= '0';
165 
166  end if;
167 
168  end process master_control;
169 
171  slave_0_control : process(tb_clk, tb_reset, slave_0_pending)
172  begin
173 
174  if(tb_reset = '1') then
175 
176  slave_0_done <= '0';
177 
178  elsif(tb_clk'event and slave_0_pending = '0') then
179 
180  slave_0_done <= '0';
181 
182  elsif(tb_clk'event and slave_0_pending = '1') then
183 
184  if(slave_0_read_write = '0') then
185  slave_0_data <= slave_0_address;
186  end if;
187 
188  slave_0_done <= '1';
189 
190  end if;
191 
192  end process slave_0_control;
193 
195  slave_1_control : process(tb_clk, tb_reset, slave_1_pending)
196  begin
197 
198  if(tb_reset = '1') then
199 
200  slave_1_done <= '0';
201 
202  elsif(tb_clk'event and slave_1_pending = '0') then
203 
204  slave_1_done <= '0';
205 
206  elsif(tb_clk'event and slave_1_pending = '1') then
207 
208  if(slave_1_read_write = '0') then
209  slave_1_data <= slave_1_address;
210  end if;
211 
212  slave_1_done <= '1';
213 
214  end if;
215 
216  end process slave_1_control;
217 
218 
219  --
220  -- Entity declarations.
221  --
222 
224  entity_master : tim_bus_master port map(
225  clk => tb_clk,
226  reset => tb_reset,
227 
228  bus_lines => bus_lines,
229  bus_valid => bus_valid,
230  bus_enable => bus_enable,
231  bus_read_write => bus_read_write,
232 
233  req_data_lines => master_data,
234  req_address_lines => master_address,
235  req_read_write => master_read_write,
236  req_pending => master_pending,
237  req_acknowledge => master_acknowledge
238  );
239 
241  entity_slave_0 : tim_bus_slave generic map(
242  address_range_top => 1023,
243  address_range_bottom => 0
244  )
245  port map(
246  clk => tb_clk,
247  reset => tb_reset,
248 
249  bus_lines => bus_lines,
250  bus_valid => bus_valid,
251  bus_enable => bus_enable,
252  bus_read_write => bus_read_write,
253 
254  req_read_write => slave_0_read_write,
255  req_address_lines => slave_0_address ,
256  req_data_lines => slave_0_data,
257  req_pending => slave_0_pending ,
258  req_done => slave_0_done
259  );
260 
262  entity_slave_1 : tim_bus_slave generic map(
263  address_range_top => 2047,
264  address_range_bottom => 1024
265  )
266  port map(
267  clk => tb_clk,
268  reset => tb_reset,
269 
270  bus_lines => bus_lines,
271  bus_valid => bus_valid,
272  bus_enable => bus_enable,
273  bus_read_write => bus_read_write,
274 
275  req_read_write => slave_1_read_write,
276  req_address_lines => slave_1_address ,
277  req_data_lines => slave_1_data,
278  req_pending => slave_1_pending ,
279  req_done => slave_1_done
280  );
281 
282 end architecture testbench;
283 
284 
tb_bus.testbench.slave_0_control
slave_0_controltb_clk,tb_reset,slave_0_pending
Responsible for stimulating the master bus controller.
Definition: tb_bus.vhdl:171
tb_bus.testbench.slave_1_control
slave_1_controltb_clk,tb_reset,slave_1_pending
Responsible for stimulating the master bus controller.
Definition: tb_bus.vhdl:195
tim_bus_master.bus_read_write
out bus_read_writestd_logic
High if this transaction is a write, low if it is a read.
Definition: bus_master.vhdl:38
tim_bus_slave.address_range_bottom
address_range_bottominteger :=0
The bottomof the range of addresses to which this slave controller will respond to requests...
Definition: bus_slave.vhdl:26
tim_bus_slave
The bus slave controller module which responds to requests from the master.
Definition: bus_slave.vhdl:17
tim_bus_slave.bus_read_write
in bus_read_writestd_logic
High if this transaction is a write, low if it is a read.
Definition: bus_slave.vhdl:44
tb_bus.testbench.tim_bus_master
tim_bus_master
The bus master controller module which arbitrates bus requests and responses.
Definition: tb_bus.vhdl:28
entity_slave_1
tim_bus_slave entity_slave_1entity_slave_1
The second bus device.
Definition: tb_bus.vhdl:262
tim_bus_slave.req_address_lines
out req_address_linesstd_logic_vector (data_width - 1 downto 0)
The address the bus transaction is targeting within the device.
Definition: bus_slave.vhdl:50
tim_bus_master.req_read_write
in req_read_writestd_logic
Tells the controller if this is a read or write transaction. High == write, low == read...
Definition: bus_master.vhdl:44
tim_bus_slave.data_width
data_widthinteger :=tim_bus_data_width
The number of data and address lines.
Definition: bus_slave.vhdl:20
tim_bus_slave.bus_valid
in bus_validstd_logic
Used to assert data written by the bus master to bus_lines is valid.
Definition: bus_slave.vhdl:38
entity_master
tim_bus_master entity_masterentity_master
The bus master object.
Definition: tb_bus.vhdl:224
tim_bus_master.req_address_lines
in req_address_linesstd_logic_vector (data_width - 1 downto 0)
Addresses for read and write operations are placed on these lines.
Definition: bus_master.vhdl:47
tim_bus_slave.reset
in resetstd_logic
Asynchonous reset signal.
Definition: bus_slave.vhdl:32
tim_bus_master.req_pending
in req_pendingstd_logic
This is put high to tell the controller a request is pending.
Definition: bus_master.vhdl:50
tim_bus_master.reset
in resetstd_logic
Asynchonous reset signal.
Definition: bus_master.vhdl:26
tim_bus_slave.address_range_top
address_range_topinteger :=1023
The top of the range of addresses to which this slave controller will respond to requests.
Definition: bus_slave.vhdl:23
tb_bus.testbench.bus_lines
std_logic_vector (tim_bus_data_width - 1 downto 0) :=( others =>'Z' ) bus_lines
Testbench reset signal.
Definition: tb_bus.vhdl:104
entity_slave_0
tim_bus_slave entity_slave_0entity_slave_0
The First bus device.
Definition: tb_bus.vhdl:241
tim_bus_master.bus_lines
inout bus_linesstd_logic_vector (data_width - 1 downto 0)
The lines which carry data and addresses;.
Definition: bus_master.vhdl:29
tim_bus_master.clk
in clkstd_logic
The main system clock.
Definition: bus_master.vhdl:24
tim_bus_master.bus_valid
out bus_validstd_logic
Used to assert data written by the bus master to bus_lines is valid.
Definition: bus_master.vhdl:32
tb_bus.testbench.tb_reset
std_logic :='1' tb_reset
Testbench clock signal.
Definition: tb_bus.vhdl:99
tb_bus.testbench.master_control
master_controltb_clk,tb_reset,master_acknowledge
Responsible for stimulating the master bus controller.
Definition: tb_bus.vhdl:150
tim_bus_master.req_acknowledge
out req_acknowledgestd_logic
Definition: bus_master.vhdl:54
tb_bus.testbench.tb_clk
std_logic :='0' tb_clk
Tells the controller the device has written/read all values from the address and data lines and can f...
Definition: tb_bus.vhdl:97
tim_bus_master.req_data_lines
inout req_data_linesstd_logic_vector (data_width - 1 downto 0)
Request write data is placed on these lines.
Definition: bus_master.vhdl:41
tb_bus.testbench.tim_bus_slave
tim_bus_slave
This is put high to tell the requestor that the response is valid and its transaction is complete...
Definition: tb_bus.vhdl:61
tim_bus_master.data_width
data_widthinteger :=tim_bus_data_width
The number of data and address lines.
Definition: bus_master.vhdl:20
tim_bus_slave.req_read_write
out req_read_writestd_logic
Whether this is a read or write transaction the device must respond to.
Definition: bus_slave.vhdl:47
tim_bus_slave.bus_enable
out bus_enablestd_logic
Used to assert that the slave has read the bus lines and they can be updated.
Definition: bus_slave.vhdl:41
tim_bus_slave.clk
in clkstd_logic
The main system clock.
Definition: bus_slave.vhdl:30
tb_bus
Empty entity declaration of the bus testbench.
Definition: tb_bus.vhdl:19
tim_bus_slave.req_done
in req_donestd_logic
Tells the controller the device has written/read all values from the address and data lines and can f...
Definition: bus_slave.vhdl:59
tim_bus_slave.req_data_lines
inout req_data_linesstd_logic_vector (data_width - 1 downto 0)
The data the transaction needs. Either read data is put onto this or write data is taken off it...
Definition: bus_slave.vhdl:53
tim_bus_slave.req_pending
out req_pendingstd_logic
Tells the host device a bus request needs dealing with.
Definition: bus_slave.vhdl:56
tim_bus_master
The bus master controller module which arbitrates bus requests and responses.
Definition: bus_master.vhdl:17
tim_bus_slave.bus_lines
inout bus_linesstd_logic_vector (data_width - 1 downto 0)
The lines which carry data and addresses;.
Definition: bus_slave.vhdl:35
tim_bus
This package contains entity declarations and shared constant values for the bus logic modules...
Definition: bus_common.vhdl:11
tim_bus_master.bus_enable
in bus_enablestd_logic
Used to assert that the slave has read the bus lines and they can be updated.
Definition: bus_master.vhdl:35