Bus testbench architecture. More...

Processes
master_control	( tb_clk , tb_reset , master_acknowledge )
	Responsible for stimulating the master bus controller.
slave_0_control	( tb_clk , tb_reset , slave_0_pending )
	Responsible for stimulating the master bus controller.
slave_1_control	( tb_clk , tb_reset , slave_1_pending )
	Responsible for stimulating the master bus controller.

Components
tim_bus_master	<Entity tim_bus_master>
	The bus master controller module which arbitrates bus requests and responses.
tim_bus_slave	<Entity tim_bus_slave>
	This is put high to tell the requestor that the response is valid and its transaction is complete.

Signals
tb_clk	std_logic := ' 0 '
	Tells the controller the device has written/read all values from the address and data lines and can finish the request.
tb_reset	std_logic := ' 1 '
	Testbench clock signal.
bus_lines	std_logic_vector ( tim_bus_data_width - 1 downto 0 ) := ( others = > ' Z ' )
	Testbench reset signal.
bus_valid	std_logic := ' 0 '
bus_enable	std_logic := ' 0 '
bus_read_write	std_logic := ' 0 '
master_data	std_logic_vector ( tim_bus_data_width - 1 downto 0 ) := ( others = > ' 1 ' )
master_address	std_logic_vector ( tim_bus_data_width - 1 downto 0 ) := ( others = > ' 0 ' )
master_read_write	std_logic := ' 0 '
master_pending	std_logic := ' 0 '
master_acknowledge	std_logic := ' 0 '
slave_0_read_write	std_logic := ' 0 '
slave_0_address	std_logic_vector ( tim_bus_data_width - 1 downto 0 ) := ( others = > ' Z ' )
slave_0_data	std_logic_vector ( tim_bus_data_width - 1 downto 0 ) := ( others = > ' 0 ' )
slave_0_pending	std_logic := ' 0 '
slave_0_done	std_logic := ' 0 '
slave_1_read_write	std_logic := ' 0 '
slave_1_address	std_logic_vector ( tim_bus_data_width - 1 downto 0 ) := ( others = > ' Z ' )
slave_1_data	std_logic_vector ( tim_bus_data_width - 1 downto 0 ) := ( others = > ' 1 ' )
slave_1_pending	std_logic := ' 0 '
slave_1_done	std_logic := ' 0 '

Instantiations
entity_master	tim_bus_master <Entity tim_bus_master>
	The bus master object.
entity_slave_0	tim_bus_slave <Entity tim_bus_slave>
	The First bus device.
entity_slave_1	tim_bus_slave <Entity tim_bus_slave>
	The second bus device.

Detailed Description

Bus testbench architecture.

Definition at line 24 of file tb_bus.vhdl.

The documentation for this class was generated from the following file:

Processes