Design Unit List

Here is a list of all design unit members with links to the Entities they belong to:

[detail level 12]

tim_bus	This package contains entity declarations and shared constant values for the bus logic modules
tim_common	Package header for all constants, functions and types used in TIM
tim_instructions	Package that contains declarations and definitions for all instruction opcodes and their lengths
tb_bus	Empty entity declaration of the bus testbench
tb_bus.testbench	Bus testbench architecture
tim_bus_master	The bus master controller module which arbitrates bus requests and responses
tim_bus_master.tim_bus_master_rtl	RTL & synthesisable architecture of the bus master controller
tim_bus_slave	The bus slave controller module which responds to requests from the master
tim_bus_slave.tim_bus_slave_rtl	The synthesisable architecture of the tim bus slave controller