T.I.M | ISA Specification
 All Pages
ISA Instructions

Table of Contents

This page lists all of the instructions used in the ISA along with their memory layouts.

Layouts

There are several different instruction layout types. All instructions are either 1, 2, 3 or 4 bytes long. The first byte always has the same layout. The first six bits are the opcode, the next two make up the condition code. See Conditional Execution. Thus, all instructions have the following very general layout:

Opcode | CC | Optional extra arguments.
?????? | ?? | .............................

All instructions are packed together in memeory with no byte gaps. The only requirement is that they are single byte-aligned. Hence a sequence of instructions such as: 3-byte, 1-byte, 2-byte, 4-byte would be packed as below. Note a nibble is shown as one letter for conciseness.

AA AA AA BB CC CC DD DD DD DD

While the following (unpacked) 4-byte aligned sequence is invalid and its behavior unspecified:

AA AA AA 00 BB 00 00 00 CC CC 00 00 DD DD DD DD

1-Byte Instructions.

These are the simplest instructions. Usually they perform a very precise operation or collection of operations in parts of the CPU not accessable by the rest of the instruction set. Their layout is as follows:

Opcode | CC
?????? | ??

2-Byte instructions

Usually register to register operations for simple movement / value copying between registers.

Opcode | CC | Arguments
?????? | ?? | ????????

3-Byte instructions

Most instructions are 3 bytes in length. This includes all instructions with three register operands.

Opcode | CC | Arguments
?????? | ?? | ???????? | ????????

4-Byte instructions

4 Byte instructions usually include 16 bits of immediate.

Opcode | CC | Arguments
?????? | ?? | ???????? | ???????? | ????????

Conditional Execution

All instructions support conditional execution. The two bits following the opcode in every instruction are a condition code which specifies the predicate to be satisfied if the instruction is to be executed:

  • 00 - Always execute the instruction.
  • 01 - Execute if and only if the last test was TRUE.
  • 10 - Execute if and only if the last test was FALSE.
  • 11 - Execute if and only if zero flag in the Status Register is

The result of each TEST instruction is stored in the Test Result register, and updated with each subsequent TEST instruction. Note that the TEST instruction itself can also be conditionally executed, meaning complex expressions can be built from sequences of tests.

Instructions Quick Reference

Memonic Description
LOADR Load to register X from address in register Y with offset in register Z.
LOADI Load to register X from address in register Y with immediate offset.
STORI Store register X to address in register Y with offset in register Z.
STORR Store register X to address in register Y with immediate offset.
PUSH Push register X onto the top of the stack and decrement the stack pointer.
POP Pop element at top of stack into register X and increment the stack pointer.
MOVR Move the content of register X into register Y
MOVI Move immediate I into register X
JUMPR Jump to address contained within register X
JUMPI Jump to address contained within instruction immediate.
CALLR Call to function who's address is contained within register X
CALLI Call to function who's address is contained within instruction immediate.
RETURN Return from the last function call.
TEST Test two general or special registers and set comparison bits.
HALT Stop processing and wait to be reset.
ANDR Bitwise AND two registers together.
NANDR Bitwise NAND two registers together.
ORR Bitwise OR two registers together.
NORR Bitwise NOR two registers together.
XORR Bitwise XOR two registers together.
LSLR Logical shift left the bits in register X by the value in register Y.
LSRR Logical shift right the bits in register X by the value in register Y.
NOTR Bitwise invert the specificed register.
ANDI Bitwise AND two registers together.
NANDI Bitwise NAND two registers together.
ORI Bitwise OR two registers together.
NORI Bitwise NOR two registers together.
XORI Bitwise XOR two registers together.
LSLI Logical shift left the bits in register X by the immediate value
LSRI Logical shift right the bits in register X by the immediate value
IADDI Integer Add register X to immediate value.
ISUBI Integer Subtract immediate value from register X.
IMULI Integer Multiply register X by immediate value.
IDIVI Integer Divide register X by immediate value.
IASRI Integer Arithmetic shift register X right immediate value.
IADDR Integer Add register X to register Y.
ISUBR Integer Subtract register X from register Y.
IMULR Integer Multiply register X by register Y.
IDIVR Integer Divide register X by register Y.
IASRR Integer Arithmetic shift register X right value in register Y.
FADDI Floating point Add register X to immediate value.
FSUBI Floating point Subtract immediate value from register X.
FMULI Floating point Multiply register X by immediate value.
FDIVI Floating point Divide register X by immediate value.
FASRI Floating point Arithmetic shift register X right immediate value.
FADDR Floating point Add register X to register Y.
FSUBR Floating point Subtract register X from register Y.
FMULR Floating point Multiply register X by register Y.
FDIVR Floating point Divide register X by register Y.
FASRR Floating point Arithmetic shift register X right value in register Y.