T.I.M | ISA Specification
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STORR

Description

Stores a value from the source register into memory. The address used is the summation of the second and third operand registers. The contents of the second and third registers are treated as unsigned 4-byte aligned numbers. The final nibble of the instruction is a byte mask used to set which bytes are actually stored to memory and which are discarded.

Register Access

The STORR instruction can use any of the general purpose registers R0 to R15 as either destination or source operands.

Memory Layout

This is a 3 byte instruction

Opcode | Condition Code | Destination | Source 1 | Source 2 | Bitmask
000100 | 00 | DDDD | RRRR | rrrr | bbbb

Assembly Code Examples

Note that the final byte mask is optional. If it is omitted (as in example 3) then it is assumed to be 1111. It should be 4 characters long and only '1' or '0'.

1. | STORE $R0 $R1 $R3 1111 ; Store all bits in R0
2. | STORE $R7 $R14 $R13 1100 ; Store the upper 16 bits from R7
3. | STORE $R5 $R5 $R6
See Also
Instructions Quick Reference, STORI