This project aims to provide a Doxygen-like tool for the Verilog Hardware Description Language (HDL).
It is currently under heavy development, and in the early stages of construction. None the less, it can parse input source trees and spit out a module hierarchy and file list, as well as document a modules ports.
A demonstration documentation build, as of commit 41a873c, can be found here. It uses the OpenSPARC T1 microprocessor from Oracle as the input code.