My name is Ben
I am an engineer.
My background is in CPU design and hardware verification.
as a Researcher at the
University of Bristol.
I develop ways of building CPUs to securely and efficiently execute
cryptographic workloads, and study how to defend them against side-channel
You can find me on
(if you must)
Marshall, B., Newell, G. R., Page, D., Saarinen, M.-J. O., & Wolf, C. (2020).
The design of scalar AES Instruction Set Extensions for RISC-V. IACR
Transactions on Cryptographic Hardware and Embedded Systems, 2021(1), 109-136.
Ben Marshall, Dan Page and Thinh Pham.
Implementing the Draft RISC-V Scalar Cryptography Extensions.
Proceedings of the 9th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP'20).
Markku-Juhani O. Saarinen, G. Richard Newell, and Ben Marshall.
Building a Modern TRNG: An Entropy Source Interface for RISC-V.
In 4th Workshop on Attacks and Solutions in Hardware Security (ASHES'20).
Gao, S., Marshall, B., Page, D. and Pham, T.,
FENL: an ISE to mitigate analogue micro-architectural leakage.
IACR Transactions on Cryptographic Hardware and Embedded Systems, pp.73-98.
Gao, S., Marshall, B., Page, D. and Oswald, E.,
Share-slicing: Friend or Foe?.
IACR Transactions on Cryptographic Hardware and Embedded Systems, pp.152-174.
On Hardware Verification In An Open Source Context
Workshop on Open Source Design Automation (OSDA) 2019
Letters & Writing: