T.I.M
A Tiny Instruction Machine Written In VHDL.
TIM is a very simple RISC CPU implemented in VHDL and designed to be synthesisable onto an FPGA.
Eventually the project will contain a fully documented micro-architecture consisting of:
- A full CPU implemented in VHDL with accompanying test benches.
- A small set of associated hardware modules to make it easy to connect to RAM blocks. This will be the method by which programs are loaded, sourced and exectuted.
- A complete assembler along with the documented ISA. This will target either raw binary to be executed on the synthesised hardware or VHDL bus files for simulation and testing.
- A high level language compiler to target the ISA. This might take a while though!
- Example test programs and hopefully a little interactive demo.
Documentation is split between hardware and software. Hardware contains the HDL modules that make up the actual CPU and peripherals. Software contains the tests, assembler, compiler and any other programs used to run the CPU.
Note that this will change ALOT because the project is at such an early stage. Please dont hurt yourself by studying it too closely at the moment! You can also track the progress of the project on GitHub